Är det något som har bytt till bättre klockan på ett Hantek/Tekway DSO oscilloskop?
Läste denna tråd på eevblog:
http://www.eevblog.com/forum/testgear/h ... /620/?wap2
Klippt från bloggen:
Btw, someone asked already before if there is a chance to reduce the waveform interferences,
well actually yes. By default the HanTekway DSOs are using standard quarz oscillators,
from all the models/hardware revisions over the time i know they typically specified somewhere
between 150ps up to 250ps total jitter. The FPGA pin (clock output to ADCs) jitter, as already mentioned in Rigol thread
is constant - however the calculation is based on the input clock quality (which is coming from the quarz oscillator).
This means if the clock signal have 30ps total jitter we have max 650ps jitter on ADC clock,
with 250ps input clock jitter you can calculate how the ADC clock looks like.
I did replaced my quarz oscillator, by low jitter model - FXO-HC736R-100 from Fox Electronics (digikey 631-1176-1-ND),
this baby have only ~25ps total jitter which is already below Altera specs.
However, it is not enough to change this part, the factory calibration need to be executed / re-created.
Therefore i looked around and found that Tekway/Hantek implemented the factory calibration procedure
into the firmware, as a hidden menu.
Det jag är mest är nyfiken på är när man mäter jitter "Eye pattern" med oscilloskopet så borde väl den interna klocka sätta noggrannheten/upplösning pga eget jitter!?
