Om men med ett DDR SDRAM chip har rätt "row" öppen och lägger ut ett läskommando så får man vänta "CAS Latency" klockcykler innan man får ut datat. Säg att CL är 3 och burst length är 8 om man då lägger in ett läskommando 3 klockcykler innan sista datat lästs ut. Slipper man vänta på nästa omgång av 8 ord ..?
(ord = bitbredd som minneschippet jobbar med, t.ex 4-8-16-32 bitar)
DRAM timing CAS-till-CAS
Re: DRAM timing CAS-till-CAS
Hittade svaret 
http://www.yale.edu/pclt/PCHW/memories.htm
"Of course, memory performance would suffer if you had to wait 5 cycles between every burst. Fortunately, access within a row can be "pipelined". You don't have to wait for a previous memory request to end before presenting the next address for the next chunk of data. The memory can be locating the next data in the row while it is transferring the previous burst of data."
http://www.yale.edu/pclt/PCHW/memories.htm
"Of course, memory performance would suffer if you had to wait 5 cycles between every burst. Fortunately, access within a row can be "pipelined". You don't have to wait for a previous memory request to end before presenting the next address for the next chunk of data. The memory can be locating the next data in the row while it is transferring the previous burst of data."
