Kod: Markera allt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD is
Port ( E : out STD_LOGIC;
RS : out STD_LOGIC;
DATA : inout STD_LOGIC_VECTOR (7 downto 0);
RW : inout STD_LOGIC;
CS1 : out STD_LOGIC;
CS2 : out STD_LOGIC;
clka : in STD_LOGIC;
status : out STD_LOGIC_VECTOR(4 downto 0));
end LCD;
architecture Behavioral of LCD is
signal delay : integer := 0;
signal done_sendning : STD_LOGIC;
signal wait_for : STD_LOGIC;
signal e_strobe_res : STD_LOGIC;
signal CMD : STD_LOGIC_VECTOR(8 downto 0); -- 8: (0 = Kommando, 1 = Data)
signal IP: integer := 0;
signal tempsig: STD_LOGIC_VECTOR(5 downto 0);
signal init_next_half: STD_LOGIC;
begin
e_strobe: process (clka, wait_for)
begin
if (wait_for = '1') then
if (clka'event and clka='1') then
E <= '1';
delay <= delay + 1;
if (delay >= 22500) then --0,00045 / 0,00000002 = 22500 (450 ns min)
E <= '0';
if (delay = 45000) then
delay <= 0;
e_strobe_res <= '0';
end if;
end if;
end if;
end if;
end process e_strobe;
sendCMD_D: process (CMD)
begin
if CMD > "000000000" then
done_sendning <= '0';
RW <= '1';
RS <= '0'; -- Läser status...
while DATA(7) = '1' loop
wait_for <= '1';
end loop;
if DATA(7) = '1' then
RW <= '0';
DATA(7 downto 0) <= CMD (7 downto 0);
RS <= CMD(8) and '1';
wait_for <= '1';
if e_strobe_res = '0' then
done_sendning <= '1';
end if;
end if;
end if;
end process sendCMD_D;
state_machine: process
subtype rom_word is STD_LOGIC_VECTOR(3 downto 0);
type rom_table is array(0 to 10) of rom_word;
constant State_rom: rom_table := rom_table'("0001","0000","0010","0101",
"0100","0110","1001","0111",
"0011","1011","1101");
begin
status(3 downto 0) <= State_rom(IP);
case State_rom(IP)(0) is
when '0' => --- Skicka kommando
CMD(8) <= '0';
case State_rom(IP)(3 downto 1) is
when "000" => CMD(7 downto 0) <= X"3F"; -- Sätter på display(X) utpekad av CSx
when "001" => CMD(7 downto 0) <= X"C0"; -- Sätter start linje
when "010" => CMD(7 downto 0) <= (X"B8" or ("00" & (tempsig and "111111")));
when "011" => CMD(7 downto 0) <= X"40";
when others => IP <= IP - 1;
end case;
if done_sendning = '1' then -- Behöver bara kolla denna bit
IP <= IP + 1;
end if;
when '1' => -- Gör någonting annat...
case State_rom(IP)(3 downto 1) is
when "000" => CS1 <= '1'; -- Markera CS1
CS2 <= '0';
IP <= IP + 1;
when "001" => CS1 <= '0'; -- Makera CS2
CS2 <= '1';
IP <= IP + 1;
when "010" => tempsig <= "001000";
IP <= IP + 1;
when "011" => tempsig <= tempsig - 1;
if (tempsig = 0) then
IP <= IP + 1;
else
IP <= IP - 3;
end if;
when "100" => tempsig <= "000000";
while (tempsig < "111111") loop
CMD(8 downto 0) <= "111111111";
if done_sendning = '1' then
tempsig <= tempsig + 1;
end if;
end loop;
when "101" => if init_next_half = '0' then
IP <= IP - 8;
init_next_half <= '1';
else
IP <= IP + 1;
end if;
when "110" => status(4) <= '1';-- Evighets loop...
when others => null
end case;
when others => null;
end case;
end process state_machine;
end Behavioral;
Kod: Markera allt
NET "E" LOC = "C11";
NET "RS" LOC = "C10";
NET "RW" LOC = "E10";
NET "DATA<0>" LOC = "D11";
NET "DATA<1>" LOC = "C12";
NET "DATA<2>" LOC = "D12";
NET "DATA<3>" LOC = "E11";
NET "DATA<4>" LOC = "B16";
NET "DATA<5>" LOC = "R3";
NET "DATA<6>" LOC = "C16";
NET "DATA<7>" LOC = "D16";
NET "CS1" LOC = "E16";
NET "CS2" LOC = "G15";
NET "status<4>" LOC = "P11";
NET "status<3>" LOC = "P12";
NET "status<2>" LOC = "N12";
NET "status<1>" LOC = "P13";
NET "status<0>" LOC = "N14";
NET "clka" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 50 MHz HIGH 50%;
NET "clka" LOC = "T9";
Någon som har nån aning om vad felet kan vara? (okej koden är nog inte den bästa så all feedback är varmt välkommen då detta är mitt typ 3:e VHDL "program")
