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There is an adjustable current limiter in parallel for the fixed output, thus supplying adjustable present source for scaled-down currents. This circuit is incredibly straightforward also. You might discover that there is no current sensing resistor. But it is definitely there, inside a type of the Rds-on resistance of the N-channel FET, which basically handles the load cutoff from the supply. The perform of the FET is proven in the diagram 2. When the existing Id is rising, the pressure Uds over the resistance Rds rises especially gradually in the starting, but especially quick immediately after the knick. This means, that just before the knick the FET behaves as being a resistor but right after it, works as continuous existing source. The D2, R3 and B-E connection of the Q4 will feeling the Uds voltage with the FET1. When the voltage rises sufficient, the Q4 will shortcut the FET1 gate to mass, and reduce the current circulation via the FET 1 off.

Nonetheless, to allow the FET1 to open, there is particular gate voltage required, which with this case is brought up through the voltage divider consisting of R8, Z1, P1 and R9. So the optimum Gate voltage will probably be the one with the Z1, along with the minimal is going to be around 3V6. The Z1 voltage (Uz1) will therefore establish the max current flowing via the FET one. The diagram two will indicate that for 5 Amps the Uz1 really should be 5V6, and for 20Amps close to 9V6.The Capacitor C4 will determine the “velocity” or the reaction time with the limiter. a hundred uF will make the response time to be about 100ms, and 1n will allow it to be 1us. Inside the created limits, the P1 will restrict the existing output within the array of 15mA to 20A.