Svenska ElektronikForumet

Kod: Markera allt

module multi(con_clk,con_din,con_dout,con_prog,con_aux1,con_aux2,mode,pp_d,
                pp_strobe,pp_ack,pp_busy,pp_pe,pp_sel,pp_error,pp_autofd,
                pp_init,pp_selin,dummy);

	inout con_clk,con_din,con_dout,con_prog,con_aux1,con_aux2;
	input [3:0] mode;
	input [7:0] pp_d;
	input pp_strobe,pp_autofd,pp_init,pp_selin;
	output reg pp_ack,pp_busy,pp_pe,pp_sel,pp_error;

	reg con_clk_,con_din_,con_dout_,con_prog_,con_aux1_,con_aux2_;

	assign con_clk = con_clk_;
	assign con_din = con_din_;
	assign con_dout = con_dout_;
	assign con_prog = con_prog_;
	assign con_aux1 = con_aux1_;
	assign con_aux2 = con_aux2_;

	parameter XILINX = 4'h1; // Xilinx parallel cable III

	always@(*)
	begin
		case(mode)
			XILINX:
			begin
				con_aux1_ <= 1'bz;
				con_aux2_ <= 1'bz;
				if(pp_d[3] == 1'b0) // CTRL
				begin
					con_dout_ <= pp_d[0];
					con_clk_ <= pp_d[1];
					con_prog_ <= pp_d[2];
				end
				else
				begin
					con_dout_ <= 1'bz;
					con_clk_ <= 1'bz;
					con_prog_ <= 1'bz;
				end
				if(pp_d[4] == 1'b0)
					con_din_ <= 1'b0;
				else
					con_din_ <= 1'bz;

				pp_error <= 1'b1; // VCC_SENSE
				pp_sel <= con_din;

				pp_pe <= pp_d[6];  // loopbacks
				pp_busy <= pp_d[6];
			end
		
			default:
			begin
				con_clk_ <= 1'bz;
				con_din_ <= 1'bz;
				con_dout_ <= 1'bz;
				con_prog_ <= 1'bz;
				con_aux1_ <= 1'bz;
				con_aux2_ <= 1'bz;
				pp_ack <= 1'bz;
				pp_busy <= 1'bz;
				pp_pe <= 1'bz;
				pp_sel <= 1'bz;
				pp_error <= 1'bz;
			end
		endcase		
	end

endmodule