Jag är dock intresserad av att pinnarna aldrig ändras, det kan bli grova missar när jag lägger allt på ett kretskort, så jag gjorde en
constraint-fil för att mappa pinnarna till exakt de ställen som programvarorna själv valde (när jag fick gröna bockar överallt).
Saxad info från fitter-rapporten innan jag lagt på en constraint:
Kod: Markera allt
Signal Total Total Bank Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
PB<0> 1 5 2 FB1_1 38 I/O O LVTTL FAST
PB<10> 1 5 2 FB1_2 37 I/O O LVTTL FAST
PB<1> 1 5 2 FB1_3 36 I/O O LVTTL FAST
PB<2> 1 5 2 FB1_4 34 GTS/I/O O LVTTL FAST
PB<3> 1 5 2 FB1_5 33 GTS/I/O O LVTTL FAST
PB<4> 1 5 2 FB1_6 32 GTS/I/O O LVTTL FAST
PB<5> 1 5 2 FB1_7 31 GTS/I/O O LVTTL FAST
PB<6> 1 5 2 FB1_8 30 GSR/I/O O LVTTL FAST
PB<7> 1 5 2 FB1_9 29 I/O O LVTTL FAST
PB<8> 1 5 2 FB1_10 28 I/O O LVTTL FAST
PB<9> 1 5 2 FB1_11 27 I/O O LVTTL FAST
** 1 Buried Nodes **
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
N_PZ_18 8 12 FB1_16
** 16 Inputs **
Signal Bank Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
PA<0> 2 FB1_12 23 I/O I LVTTL KPR
PA<1> 2 FB1_13 22 I/O I LVTTL KPR
PA<2> 2 FB1_14 21 I/O I LVTTL KPR
PA<3> 2 FB1_15 20 I/O I LVTTL KPR
PA<4> 2 FB1_16 19 I/O I LVTTL KPR
PA<5> 1 FB2_1 39 I/O I LVTTL KPR
PA<6> 1 FB2_2 40 I/O I LVTTL KPR
PA<7> 1 FB2_3 41 I/O I LVTTL KPR
enable 1 FB2_4 42 I/O I LVTTL KPR
sel<0> 1 FB2_5 43 GCK/I/O I LVTTL KPR
sel<1> 1 FB2_6 44 GCK/I/O I LVTTL KPR
sel<2> 1 FB2_7 1 GCK/I/O I LVTTL KPR
sel<3> 1 FB2_8 2 I/O I LVTTL KPR
sel<4> 1 FB2_9 3 I/O I LVTTL KPR
sel<5> 1 FB2_10 5 I/O I LVTTL KPR
sel<6> 1 FB2_11 6 I/O I LVTTL KPR
Kod: Markera allt
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'Main.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'sel<0>' based upon the LOC
constraint 'P43'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'sel<1>' based upon the LOC
constraint 'P44'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'sel<2>' based upon the LOC
constraint 'P1'. It is recommended that you declare this BUFG explicitedly in
your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'sel_2_IBUF'
is ignored. Most likely the signal is gated and therefore cannot be used as a
global control signal.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'sel_1_IBUF'
is ignored. Most likely the signal is gated and therefore cannot be used as a
global control signal.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'sel_0_IBUF'
is ignored. Most likely the signal is gated and therefore cannot be used as a
global control signal.